/* SPDX-License-Identifier: GPL-2.0+ */
// $Module: reg_PHY_PINMUX_REG $
// $RegisterBank Version: v1.0.00 $
// $Author:  $
// $Date: Tue, 28 Feb 2023 09:49:00 AM $
//

//GEN REG ADDR/OFFSET/MASK
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0P  0x0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0N  0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1P  0x8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1N  0xc
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2P  0x10
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2N  0x14
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3P  0x18
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3N  0x1c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4P  0x20
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4N  0x24
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5P  0x28
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5N  0x2c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6P  0x30
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6N  0x34
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7P  0x38
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7N  0x3c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8P  0x40
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8N  0x44
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9P  0x48
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9N  0x4c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10P  0x50
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10N  0x54
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11P  0x58
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11N  0x5c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12P  0x60
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12N  0x64
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13P  0x68
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13N  0x6c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14P  0x70
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14N  0x74
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15P  0x78
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15N  0x7c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16P  0x80
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16N  0x84
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17P  0x88
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17N  0x8c
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0P  0x90
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0N  0x94
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1P  0x98
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1N  0x9c
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2P  0xa0
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2N  0xa4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3P  0xa8
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3N  0xac
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4P  0xb0
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4N  0xb4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0P  0xb8
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0N  0xbc
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1P  0xc0
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1N  0xc4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2P  0xc8
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2N  0xcc
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3P  0xd0
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3N  0xd4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4P  0xd8
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4N  0xdc
#define  PHY_PINMUX_REG_REG_PAD_AINL0_MIC  0xe8
#define  PHY_PINMUX_REG_REG_PAD_AINR0_MIC  0xec
#define  PHY_PINMUX_REG_REG_PAD_AINL1_MIC  0xf0
#define  PHY_PINMUX_REG_REG_PAD_AINR1_MIC  0xf4
#define  PHY_PINMUX_REG_REG_PAD_AOUTL0  0xe0
#define  PHY_PINMUX_REG_REG_PAD_AOUTR0  0xe4
#define  PHY_PINMUX_REG_REG_PAD_AOUTL1  0xf8
#define  PHY_PINMUX_REG_REG_PAD_AOUTR1  0xfc
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0P_P_EN   0x0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0P_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0P_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0P_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0P_PU_SEL   0x0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0P_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0P_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0P_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0P_PIN_SEL_EN   0x0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0P_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0P_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0P_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0P_DRI_SEL   0x0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0P_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0P_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0P_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0P_SCT_EN   0x0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0P_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0P_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0P_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0P_OEX_EN   0x0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0P_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0P_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0P_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0N_P_EN   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0N_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0N_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0N_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0N_PU_SEL   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0N_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0N_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0N_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0N_PIN_SEL_EN   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0N_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0N_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0N_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0N_DRI_SEL   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0N_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0N_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0N_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0N_SCT_EN   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0N_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0N_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0N_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0N_OEX_EN   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0N_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0N_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX0N_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1P_P_EN   0x8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1P_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1P_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1P_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1P_PU_SEL   0x8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1P_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1P_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1P_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1P_PIN_SEL_EN   0x8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1P_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1P_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1P_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1P_DRI_SEL   0x8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1P_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1P_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1P_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1P_SCT_EN   0x8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1P_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1P_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1P_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1P_OEX_EN   0x8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1P_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1P_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1P_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1N_P_EN   0xc
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1N_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1N_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1N_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1N_PU_SEL   0xc
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1N_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1N_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1N_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1N_PIN_SEL_EN   0xc
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1N_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1N_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1N_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1N_DRI_SEL   0xc
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1N_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1N_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1N_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1N_SCT_EN   0xc
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1N_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1N_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1N_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1N_OEX_EN   0xc
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1N_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1N_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX1N_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2P_P_EN   0x10
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2P_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2P_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2P_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2P_PU_SEL   0x10
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2P_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2P_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2P_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2P_PIN_SEL_EN   0x10
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2P_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2P_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2P_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2P_DRI_SEL   0x10
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2P_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2P_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2P_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2P_SCT_EN   0x10
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2P_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2P_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2P_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2P_OEX_EN   0x10
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2P_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2P_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2P_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2N_P_EN   0x14
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2N_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2N_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2N_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2N_PU_SEL   0x14
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2N_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2N_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2N_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2N_PIN_SEL_EN   0x14
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2N_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2N_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2N_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2N_DRI_SEL   0x14
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2N_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2N_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2N_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2N_SCT_EN   0x14
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2N_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2N_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2N_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2N_OEX_EN   0x14
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2N_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2N_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX2N_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3P_P_EN   0x18
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3P_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3P_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3P_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3P_PU_SEL   0x18
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3P_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3P_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3P_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3P_PIN_SEL_EN   0x18
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3P_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3P_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3P_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3P_DRI_SEL   0x18
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3P_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3P_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3P_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3P_SCT_EN   0x18
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3P_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3P_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3P_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3P_OEX_EN   0x18
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3P_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3P_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3P_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3N_P_EN   0x1c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3N_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3N_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3N_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3N_PU_SEL   0x1c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3N_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3N_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3N_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3N_PIN_SEL_EN   0x1c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3N_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3N_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3N_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3N_DRI_SEL   0x1c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3N_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3N_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3N_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3N_SCT_EN   0x1c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3N_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3N_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3N_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3N_OEX_EN   0x1c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3N_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3N_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX3N_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4P_P_EN   0x20
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4P_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4P_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4P_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4P_PU_SEL   0x20
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4P_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4P_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4P_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4P_PIN_SEL_EN   0x20
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4P_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4P_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4P_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4P_DRI_SEL   0x20
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4P_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4P_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4P_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4P_SCT_EN   0x20
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4P_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4P_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4P_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4P_OEX_EN   0x20
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4P_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4P_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4P_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4N_P_EN   0x24
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4N_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4N_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4N_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4N_PU_SEL   0x24
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4N_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4N_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4N_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4N_PIN_SEL_EN   0x24
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4N_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4N_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4N_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4N_DRI_SEL   0x24
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4N_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4N_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4N_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4N_SCT_EN   0x24
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4N_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4N_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4N_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4N_OEX_EN   0x24
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4N_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4N_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX4N_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5P_P_EN   0x28
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5P_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5P_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5P_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5P_PU_SEL   0x28
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5P_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5P_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5P_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5P_PIN_SEL_EN   0x28
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5P_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5P_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5P_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5P_DRI_SEL   0x28
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5P_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5P_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5P_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5P_SCT_EN   0x28
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5P_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5P_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5P_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5P_OEX_EN   0x28
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5P_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5P_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5P_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5N_P_EN   0x2c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5N_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5N_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5N_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5N_PU_SEL   0x2c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5N_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5N_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5N_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5N_PIN_SEL_EN   0x2c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5N_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5N_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5N_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5N_DRI_SEL   0x2c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5N_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5N_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5N_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5N_SCT_EN   0x2c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5N_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5N_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5N_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5N_OEX_EN   0x2c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5N_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5N_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX5N_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6P_P_EN   0x30
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6P_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6P_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6P_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6P_PU_SEL   0x30
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6P_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6P_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6P_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6P_PIN_SEL_EN   0x30
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6P_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6P_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6P_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6P_DRI_SEL   0x30
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6P_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6P_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6P_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6P_SCT_EN   0x30
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6P_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6P_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6P_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6P_OEX_EN   0x30
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6P_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6P_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6P_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6N_P_EN   0x34
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6N_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6N_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6N_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6N_PU_SEL   0x34
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6N_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6N_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6N_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6N_PIN_SEL_EN   0x34
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6N_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6N_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6N_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6N_DRI_SEL   0x34
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6N_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6N_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6N_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6N_SCT_EN   0x34
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6N_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6N_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6N_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6N_OEX_EN   0x34
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6N_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6N_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX6N_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7P_P_EN   0x38
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7P_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7P_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7P_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7P_PU_SEL   0x38
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7P_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7P_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7P_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7P_PIN_SEL_EN   0x38
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7P_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7P_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7P_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7P_DRI_SEL   0x38
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7P_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7P_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7P_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7P_SCT_EN   0x38
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7P_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7P_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7P_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7P_OEX_EN   0x38
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7P_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7P_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7P_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7N_P_EN   0x3c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7N_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7N_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7N_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7N_PU_SEL   0x3c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7N_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7N_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7N_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7N_PIN_SEL_EN   0x3c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7N_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7N_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7N_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7N_DRI_SEL   0x3c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7N_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7N_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7N_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7N_SCT_EN   0x3c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7N_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7N_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7N_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7N_OEX_EN   0x3c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7N_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7N_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX7N_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8P_P_EN   0x40
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8P_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8P_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8P_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8P_PU_SEL   0x40
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8P_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8P_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8P_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8P_PIN_SEL_EN   0x40
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8P_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8P_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8P_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8P_DRI_SEL   0x40
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8P_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8P_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8P_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8P_SCT_EN   0x40
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8P_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8P_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8P_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8P_OEX_EN   0x40
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8P_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8P_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8P_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8N_P_EN   0x44
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8N_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8N_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8N_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8N_PU_SEL   0x44
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8N_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8N_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8N_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8N_PIN_SEL_EN   0x44
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8N_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8N_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8N_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8N_DRI_SEL   0x44
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8N_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8N_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8N_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8N_SCT_EN   0x44
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8N_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8N_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8N_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8N_OEX_EN   0x44
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8N_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8N_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX8N_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9P_P_EN   0x48
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9P_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9P_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9P_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9P_PU_SEL   0x48
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9P_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9P_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9P_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9P_PIN_SEL_EN   0x48
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9P_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9P_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9P_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9P_DRI_SEL   0x48
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9P_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9P_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9P_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9P_SCT_EN   0x48
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9P_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9P_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9P_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9P_OEX_EN   0x48
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9P_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9P_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9P_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9N_P_EN   0x4c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9N_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9N_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9N_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9N_PU_SEL   0x4c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9N_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9N_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9N_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9N_PIN_SEL_EN   0x4c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9N_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9N_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9N_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9N_DRI_SEL   0x4c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9N_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9N_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9N_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9N_SCT_EN   0x4c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9N_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9N_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9N_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9N_OEX_EN   0x4c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9N_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9N_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX9N_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10P_P_EN   0x50
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10P_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10P_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10P_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10P_PU_SEL   0x50
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10P_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10P_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10P_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10P_PIN_SEL_EN   0x50
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10P_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10P_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10P_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10P_DRI_SEL   0x50
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10P_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10P_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10P_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10P_SCT_EN   0x50
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10P_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10P_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10P_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10P_OEX_EN   0x50
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10P_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10P_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10P_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10N_P_EN   0x54
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10N_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10N_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10N_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10N_PU_SEL   0x54
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10N_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10N_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10N_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10N_PIN_SEL_EN   0x54
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10N_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10N_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10N_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10N_DRI_SEL   0x54
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10N_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10N_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10N_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10N_SCT_EN   0x54
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10N_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10N_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10N_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10N_OEX_EN   0x54
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10N_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10N_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX10N_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11P_P_EN   0x58
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11P_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11P_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11P_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11P_PU_SEL   0x58
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11P_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11P_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11P_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11P_PIN_SEL_EN   0x58
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11P_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11P_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11P_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11P_DRI_SEL   0x58
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11P_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11P_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11P_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11P_SCT_EN   0x58
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11P_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11P_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11P_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11P_OEX_EN   0x58
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11P_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11P_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11P_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11N_P_EN   0x5c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11N_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11N_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11N_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11N_PU_SEL   0x5c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11N_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11N_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11N_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11N_PIN_SEL_EN   0x5c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11N_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11N_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11N_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11N_DRI_SEL   0x5c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11N_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11N_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11N_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11N_SCT_EN   0x5c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11N_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11N_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11N_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11N_OEX_EN   0x5c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11N_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11N_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX11N_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12P_P_EN   0x60
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12P_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12P_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12P_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12P_PU_SEL   0x60
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12P_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12P_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12P_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12P_PIN_SEL_EN   0x60
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12P_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12P_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12P_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12P_DRI_SEL   0x60
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12P_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12P_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12P_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12P_SCT_EN   0x60
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12P_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12P_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12P_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12P_OEX_EN   0x60
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12P_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12P_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12P_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12N_P_EN   0x64
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12N_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12N_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12N_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12N_PU_SEL   0x64
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12N_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12N_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12N_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12N_PIN_SEL_EN   0x64
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12N_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12N_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12N_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12N_DRI_SEL   0x64
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12N_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12N_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12N_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12N_SCT_EN   0x64
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12N_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12N_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12N_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12N_OEX_EN   0x64
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12N_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12N_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX12N_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13P_P_EN   0x68
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13P_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13P_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13P_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13P_PU_SEL   0x68
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13P_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13P_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13P_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13P_PIN_SEL_EN   0x68
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13P_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13P_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13P_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13P_DRI_SEL   0x68
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13P_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13P_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13P_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13P_SCT_EN   0x68
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13P_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13P_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13P_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13P_OEX_EN   0x68
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13P_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13P_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13P_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13N_P_EN   0x6c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13N_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13N_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13N_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13N_PU_SEL   0x6c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13N_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13N_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13N_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13N_PIN_SEL_EN   0x6c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13N_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13N_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13N_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13N_DRI_SEL   0x6c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13N_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13N_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13N_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13N_SCT_EN   0x6c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13N_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13N_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13N_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13N_OEX_EN   0x6c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13N_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13N_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX13N_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14P_P_EN   0x70
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14P_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14P_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14P_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14P_PU_SEL   0x70
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14P_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14P_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14P_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14P_PIN_SEL_EN   0x70
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14P_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14P_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14P_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14P_DRI_SEL   0x70
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14P_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14P_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14P_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14P_SCT_EN   0x70
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14P_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14P_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14P_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14P_OEX_EN   0x70
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14P_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14P_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14P_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14N_P_EN   0x74
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14N_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14N_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14N_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14N_PU_SEL   0x74
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14N_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14N_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14N_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14N_PIN_SEL_EN   0x74
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14N_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14N_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14N_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14N_DRI_SEL   0x74
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14N_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14N_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14N_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14N_SCT_EN   0x74
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14N_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14N_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14N_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14N_OEX_EN   0x74
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14N_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14N_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX14N_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15P_P_EN   0x78
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15P_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15P_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15P_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15P_PU_SEL   0x78
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15P_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15P_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15P_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15P_PIN_SEL_EN   0x78
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15P_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15P_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15P_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15P_DRI_SEL   0x78
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15P_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15P_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15P_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15P_SCT_EN   0x78
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15P_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15P_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15P_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15P_OEX_EN   0x78
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15P_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15P_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15P_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15N_P_EN   0x7c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15N_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15N_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15N_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15N_PU_SEL   0x7c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15N_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15N_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15N_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15N_PIN_SEL_EN   0x7c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15N_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15N_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15N_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15N_DRI_SEL   0x7c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15N_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15N_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15N_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15N_SCT_EN   0x7c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15N_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15N_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15N_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15N_OEX_EN   0x7c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15N_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15N_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX15N_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16P_PU_EN   0x80
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16P_PU_EN_OFFSET 2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16P_PU_EN_MASK   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16P_PU_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16P_PD_EN   0x80
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16P_PD_EN_OFFSET 3
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16P_PD_EN_MASK   0x8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16P_PD_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16P_PIN_SEL_EN   0x80
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16P_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16P_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16P_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16P_DRI_SEL   0x80
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16P_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16P_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16P_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16P_SCT_EN   0x80
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16P_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16P_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16P_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16P_OEX_EN   0x80
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16P_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16P_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16P_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16N_PU_EN   0x84
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16N_PU_EN_OFFSET 2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16N_PU_EN_MASK   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16N_PU_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16N_PD_EN   0x84
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16N_PD_EN_OFFSET 3
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16N_PD_EN_MASK   0x8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16N_PD_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16N_PIN_SEL_EN   0x84
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16N_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16N_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16N_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16N_DRI_SEL   0x84
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16N_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16N_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16N_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16N_SCT_EN   0x84
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16N_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16N_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16N_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16N_OEX_EN   0x84
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16N_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16N_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX16N_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17P_P_EN   0x88
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17P_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17P_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17P_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17P_PU_SEL   0x88
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17P_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17P_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17P_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17P_PIN_SEL_EN   0x88
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17P_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17P_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17P_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17P_DRI_SEL   0x88
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17P_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17P_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17P_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17P_SCT_EN   0x88
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17P_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17P_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17P_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17P_OEX_EN   0x88
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17P_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17P_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17P_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17N_P_EN   0x8c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17N_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17N_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17N_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17N_PU_SEL   0x8c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17N_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17N_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17N_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17N_PIN_SEL_EN   0x8c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17N_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17N_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17N_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17N_DRI_SEL   0x8c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17N_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17N_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17N_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17N_SCT_EN   0x8c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17N_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17N_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17N_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17N_OEX_EN   0x8c
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17N_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17N_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI_RX17N_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0P_P_EN   0x90
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0P_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0P_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0P_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0P_PU_SEL   0x90
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0P_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0P_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0P_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0P_PIN_SEL_EN   0x90
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0P_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0P_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0P_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0P_DRI_SEL   0x90
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0P_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0P_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0P_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0P_SCT_EN   0x90
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0P_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0P_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0P_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0P_OEX_EN   0x90
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0P_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0P_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0P_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0N_P_EN   0x94
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0N_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0N_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0N_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0N_PU_SEL   0x94
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0N_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0N_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0N_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0N_PIN_SEL_EN   0x94
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0N_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0N_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0N_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0N_DRI_SEL   0x94
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0N_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0N_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0N_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0N_SCT_EN   0x94
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0N_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0N_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0N_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0N_OEX_EN   0x94
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0N_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0N_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX0N_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1P_P_EN   0x98
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1P_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1P_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1P_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1P_PU_SEL   0x98
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1P_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1P_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1P_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1P_PIN_SEL_EN   0x98
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1P_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1P_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1P_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1P_DRI_SEL   0x98
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1P_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1P_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1P_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1P_SCT_EN   0x98
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1P_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1P_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1P_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1P_OEX_EN   0x98
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1P_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1P_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1P_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1N_P_EN   0x9c
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1N_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1N_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1N_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1N_PU_SEL   0x9c
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1N_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1N_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1N_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1N_PIN_SEL_EN   0x9c
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1N_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1N_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1N_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1N_DRI_SEL   0x9c
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1N_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1N_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1N_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1N_SCT_EN   0x9c
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1N_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1N_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1N_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1N_OEX_EN   0x9c
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1N_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1N_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX1N_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2P_P_EN   0xa0
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2P_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2P_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2P_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2P_PU_SEL   0xa0
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2P_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2P_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2P_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2P_PIN_SEL_EN   0xa0
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2P_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2P_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2P_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2P_DRI_SEL   0xa0
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2P_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2P_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2P_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2P_SCT_EN   0xa0
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2P_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2P_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2P_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2P_OEX_EN   0xa0
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2P_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2P_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2P_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2N_P_EN   0xa4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2N_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2N_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2N_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2N_PU_SEL   0xa4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2N_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2N_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2N_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2N_PIN_SEL_EN   0xa4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2N_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2N_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2N_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2N_DRI_SEL   0xa4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2N_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2N_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2N_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2N_SCT_EN   0xa4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2N_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2N_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2N_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2N_OEX_EN   0xa4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2N_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2N_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX2N_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3P_PU_EN   0xa8
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3P_PU_EN_OFFSET 2
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3P_PU_EN_MASK   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3P_PU_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3P_PD_EN   0xa8
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3P_PD_EN_OFFSET 3
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3P_PD_EN_MASK   0x8
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3P_PD_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3P_PIN_SEL_EN   0xa8
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3P_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3P_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3P_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3P_DRI_SEL   0xa8
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3P_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3P_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3P_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3P_SCT_EN   0xa8
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3P_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3P_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3P_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3P_OEX_EN   0xa8
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3P_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3P_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3P_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3N_PU_EN   0xac
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3N_PU_EN_OFFSET 2
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3N_PU_EN_MASK   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3N_PU_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3N_PD_EN   0xac
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3N_PD_EN_OFFSET 3
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3N_PD_EN_MASK   0x8
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3N_PD_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3N_PIN_SEL_EN   0xac
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3N_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3N_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3N_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3N_DRI_SEL   0xac
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3N_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3N_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3N_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3N_SCT_EN   0xac
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3N_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3N_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3N_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3N_OEX_EN   0xac
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3N_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3N_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX3N_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4P_P_EN   0xb0
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4P_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4P_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4P_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4P_PU_SEL   0xb0
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4P_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4P_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4P_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4P_PIN_SEL_EN   0xb0
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4P_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4P_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4P_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4P_DRI_SEL   0xb0
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4P_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4P_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4P_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4P_SCT_EN   0xb0
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4P_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4P_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4P_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4P_OEX_EN   0xb0
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4P_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4P_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4P_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4N_P_EN   0xb4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4N_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4N_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4N_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4N_PU_SEL   0xb4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4N_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4N_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4N_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4N_PIN_SEL_EN   0xb4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4N_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4N_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4N_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4N_DRI_SEL   0xb4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4N_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4N_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4N_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4N_SCT_EN   0xb4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4N_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4N_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4N_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4N_OEX_EN   0xb4
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4N_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4N_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI0_TX4N_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0P_P_EN   0xb8
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0P_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0P_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0P_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0P_PU_SEL   0xb8
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0P_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0P_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0P_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0P_PIN_SEL_EN   0xb8
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0P_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0P_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0P_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0P_DRI_SEL   0xb8
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0P_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0P_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0P_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0P_SCT_EN   0xb8
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0P_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0P_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0P_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0P_OEX_EN   0xb8
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0P_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0P_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0P_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0N_P_EN   0xbc
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0N_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0N_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0N_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0N_PU_SEL   0xbc
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0N_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0N_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0N_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0N_PIN_SEL_EN   0xbc
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0N_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0N_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0N_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0N_DRI_SEL   0xbc
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0N_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0N_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0N_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0N_SCT_EN   0xbc
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0N_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0N_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0N_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0N_OEX_EN   0xbc
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0N_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0N_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX0N_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1P_P_EN   0xc0
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1P_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1P_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1P_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1P_PU_SEL   0xc0
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1P_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1P_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1P_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1P_PIN_SEL_EN   0xc0
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1P_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1P_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1P_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1P_DRI_SEL   0xc0
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1P_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1P_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1P_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1P_SCT_EN   0xc0
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1P_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1P_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1P_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1P_OEX_EN   0xc0
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1P_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1P_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1P_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1N_P_EN   0xc4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1N_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1N_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1N_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1N_PU_SEL   0xc4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1N_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1N_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1N_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1N_PIN_SEL_EN   0xc4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1N_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1N_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1N_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1N_DRI_SEL   0xc4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1N_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1N_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1N_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1N_SCT_EN   0xc4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1N_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1N_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1N_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1N_OEX_EN   0xc4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1N_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1N_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX1N_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2P_P_EN   0xc8
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2P_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2P_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2P_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2P_PU_SEL   0xc8
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2P_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2P_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2P_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2P_PIN_SEL_EN   0xc8
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2P_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2P_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2P_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2P_DRI_SEL   0xc8
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2P_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2P_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2P_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2P_SCT_EN   0xc8
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2P_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2P_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2P_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2P_OEX_EN   0xc8
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2P_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2P_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2P_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2N_P_EN   0xcc
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2N_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2N_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2N_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2N_PU_SEL   0xcc
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2N_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2N_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2N_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2N_PIN_SEL_EN   0xcc
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2N_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2N_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2N_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2N_DRI_SEL   0xcc
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2N_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2N_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2N_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2N_SCT_EN   0xcc
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2N_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2N_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2N_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2N_OEX_EN   0xcc
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2N_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2N_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX2N_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3P_PU_EN   0xd0
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3P_PU_EN_OFFSET 2
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3P_PU_EN_MASK   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3P_PU_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3P_PD_EN   0xd0
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3P_PD_EN_OFFSET 3
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3P_PD_EN_MASK   0x8
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3P_PD_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3P_PIN_SEL_EN   0xd0
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3P_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3P_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3P_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3P_DRI_SEL   0xd0
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3P_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3P_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3P_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3P_SCT_EN   0xd0
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3P_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3P_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3P_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3P_OEX_EN   0xd0
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3P_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3P_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3P_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3N_PU_EN   0xd4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3N_PU_EN_OFFSET 2
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3N_PU_EN_MASK   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3N_PU_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3N_PD_EN   0xd4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3N_PD_EN_OFFSET 3
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3N_PD_EN_MASK   0x8
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3N_PD_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3N_PIN_SEL_EN   0xd4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3N_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3N_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3N_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3N_DRI_SEL   0xd4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3N_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3N_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3N_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3N_SCT_EN   0xd4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3N_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3N_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3N_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3N_OEX_EN   0xd4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3N_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3N_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX3N_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4P_P_EN   0xd8
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4P_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4P_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4P_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4P_PU_SEL   0xd8
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4P_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4P_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4P_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4P_PIN_SEL_EN   0xd8
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4P_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4P_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4P_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4P_DRI_SEL   0xd8
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4P_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4P_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4P_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4P_SCT_EN   0xd8
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4P_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4P_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4P_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4P_OEX_EN   0xd8
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4P_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4P_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4P_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4N_P_EN   0xdc
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4N_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4N_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4N_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4N_PU_SEL   0xdc
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4N_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4N_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4N_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4N_PIN_SEL_EN   0xdc
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4N_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4N_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4N_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4N_DRI_SEL   0xdc
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4N_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4N_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4N_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4N_SCT_EN   0xdc
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4N_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4N_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4N_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4N_OEX_EN   0xdc
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4N_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4N_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_MIPI1_TX4N_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_AINL0_MIC_P_EN   0xe0
#define  PHY_PINMUX_REG_REG_PAD_AINL0_MIC_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_AINL0_MIC_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_AINL0_MIC_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_AINL0_MIC_PU_SEL   0xe0
#define  PHY_PINMUX_REG_REG_PAD_AINL0_MIC_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_AINL0_MIC_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_AINL0_MIC_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_AINL0_MIC_PIN_SEL_EN   0xe0
#define  PHY_PINMUX_REG_REG_PAD_AINL0_MIC_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_AINL0_MIC_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_AINL0_MIC_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_AINL0_MIC_DRI_SEL   0xe0
#define  PHY_PINMUX_REG_REG_PAD_AINL0_MIC_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_AINL0_MIC_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_AINL0_MIC_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_AINL0_MIC_SCT_EN   0xe0
#define  PHY_PINMUX_REG_REG_PAD_AINL0_MIC_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_AINL0_MIC_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_AINL0_MIC_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_AINL0_MIC_OEX_EN   0xe0
#define  PHY_PINMUX_REG_REG_PAD_AINL0_MIC_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_AINL0_MIC_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_AINL0_MIC_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_AINR0_MIC_P_EN   0xe4
#define  PHY_PINMUX_REG_REG_PAD_AINR0_MIC_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_AINR0_MIC_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_AINR0_MIC_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_AINR0_MIC_PU_SEL   0xe4
#define  PHY_PINMUX_REG_REG_PAD_AINR0_MIC_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_AINR0_MIC_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_AINR0_MIC_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_AINR0_MIC_PIN_SEL_EN   0xe4
#define  PHY_PINMUX_REG_REG_PAD_AINR0_MIC_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_AINR0_MIC_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_AINR0_MIC_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_AINR0_MIC_DRI_SEL   0xe4
#define  PHY_PINMUX_REG_REG_PAD_AINR0_MIC_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_AINR0_MIC_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_AINR0_MIC_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_AINR0_MIC_SCT_EN   0xe4
#define  PHY_PINMUX_REG_REG_PAD_AINR0_MIC_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_AINR0_MIC_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_AINR0_MIC_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_AINR0_MIC_OEX_EN   0xe4
#define  PHY_PINMUX_REG_REG_PAD_AINR0_MIC_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_AINR0_MIC_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_AINR0_MIC_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_AINL1_MIC_P_EN   0xe8
#define  PHY_PINMUX_REG_REG_PAD_AINL1_MIC_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_AINL1_MIC_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_AINL1_MIC_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_AINL1_MIC_PU_SEL   0xe8
#define  PHY_PINMUX_REG_REG_PAD_AINL1_MIC_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_AINL1_MIC_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_AINL1_MIC_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_AINL1_MIC_PIN_SEL_EN   0xe8
#define  PHY_PINMUX_REG_REG_PAD_AINL1_MIC_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_AINL1_MIC_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_AINL1_MIC_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_AINL1_MIC_DRI_SEL   0xe8
#define  PHY_PINMUX_REG_REG_PAD_AINL1_MIC_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_AINL1_MIC_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_AINL1_MIC_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_AINL1_MIC_SCT_EN   0xe8
#define  PHY_PINMUX_REG_REG_PAD_AINL1_MIC_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_AINL1_MIC_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_AINL1_MIC_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_AINL1_MIC_OEX_EN   0xe8
#define  PHY_PINMUX_REG_REG_PAD_AINL1_MIC_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_AINL1_MIC_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_AINL1_MIC_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_AINR1_MIC_P_EN   0xec
#define  PHY_PINMUX_REG_REG_PAD_AINR1_MIC_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_AINR1_MIC_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_AINR1_MIC_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_AINR1_MIC_PU_SEL   0xec
#define  PHY_PINMUX_REG_REG_PAD_AINR1_MIC_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_AINR1_MIC_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_AINR1_MIC_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_AINR1_MIC_PIN_SEL_EN   0xec
#define  PHY_PINMUX_REG_REG_PAD_AINR1_MIC_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_AINR1_MIC_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_AINR1_MIC_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_AINR1_MIC_DRI_SEL   0xec
#define  PHY_PINMUX_REG_REG_PAD_AINR1_MIC_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_AINR1_MIC_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_AINR1_MIC_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_AINR1_MIC_SCT_EN   0xec
#define  PHY_PINMUX_REG_REG_PAD_AINR1_MIC_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_AINR1_MIC_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_AINR1_MIC_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_AINR1_MIC_OEX_EN   0xec
#define  PHY_PINMUX_REG_REG_PAD_AINR1_MIC_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_AINR1_MIC_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_AINR1_MIC_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_AOUTL0_P_EN   0xf0
#define  PHY_PINMUX_REG_REG_PAD_AOUTL0_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_AOUTL0_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_AOUTL0_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_AOUTL0_PU_SEL   0xf0
#define  PHY_PINMUX_REG_REG_PAD_AOUTL0_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_AOUTL0_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_AOUTL0_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_AOUTL0_PIN_SEL_EN   0xf0
#define  PHY_PINMUX_REG_REG_PAD_AOUTL0_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_AOUTL0_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_AOUTL0_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_AOUTL0_DRI_SEL   0xf0
#define  PHY_PINMUX_REG_REG_PAD_AOUTL0_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_AOUTL0_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_AOUTL0_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_AOUTL0_SCT_EN   0xf0
#define  PHY_PINMUX_REG_REG_PAD_AOUTL0_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_AOUTL0_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_AOUTL0_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_AOUTL0_OEX_EN   0xf0
#define  PHY_PINMUX_REG_REG_PAD_AOUTL0_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_AOUTL0_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_AOUTL0_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_AOUTR0_P_EN   0xf4
#define  PHY_PINMUX_REG_REG_PAD_AOUTR0_P_EN_OFFSET 0
#define  PHY_PINMUX_REG_REG_PAD_AOUTR0_P_EN_MASK   0x1
#define  PHY_PINMUX_REG_REG_PAD_AOUTR0_P_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_AOUTR0_PU_SEL   0xf4
#define  PHY_PINMUX_REG_REG_PAD_AOUTR0_PU_SEL_OFFSET 1
#define  PHY_PINMUX_REG_REG_PAD_AOUTR0_PU_SEL_MASK   0x2
#define  PHY_PINMUX_REG_REG_PAD_AOUTR0_PU_SEL_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_AOUTR0_PIN_SEL_EN   0xf4
#define  PHY_PINMUX_REG_REG_PAD_AOUTR0_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_AOUTR0_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_AOUTR0_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_AOUTR0_DRI_SEL   0xf4
#define  PHY_PINMUX_REG_REG_PAD_AOUTR0_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_AOUTR0_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_AOUTR0_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_AOUTR0_SCT_EN   0xf4
#define  PHY_PINMUX_REG_REG_PAD_AOUTR0_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_AOUTR0_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_AOUTR0_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_AOUTR0_OEX_EN   0xf4
#define  PHY_PINMUX_REG_REG_PAD_AOUTR0_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_AOUTR0_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_AOUTR0_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_AOUTL1_PU_EN   0xf8
#define  PHY_PINMUX_REG_REG_PAD_AOUTL1_PU_EN_OFFSET 2
#define  PHY_PINMUX_REG_REG_PAD_AOUTL1_PU_EN_MASK   0x4
#define  PHY_PINMUX_REG_REG_PAD_AOUTL1_PU_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_AOUTL1_PD_EN   0xf8
#define  PHY_PINMUX_REG_REG_PAD_AOUTL1_PD_EN_OFFSET 3
#define  PHY_PINMUX_REG_REG_PAD_AOUTL1_PD_EN_MASK   0x8
#define  PHY_PINMUX_REG_REG_PAD_AOUTL1_PD_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_AOUTL1_PIN_SEL_EN   0xf8
#define  PHY_PINMUX_REG_REG_PAD_AOUTL1_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_AOUTL1_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_AOUTL1_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_AOUTL1_DRI_SEL   0xf8
#define  PHY_PINMUX_REG_REG_PAD_AOUTL1_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_AOUTL1_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_AOUTL1_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_AOUTL1_SCT_EN   0xf8
#define  PHY_PINMUX_REG_REG_PAD_AOUTL1_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_AOUTL1_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_AOUTL1_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_AOUTL1_OEX_EN   0xf8
#define  PHY_PINMUX_REG_REG_PAD_AOUTL1_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_AOUTL1_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_AOUTL1_OEX_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_AOUTR1_PU_EN   0xfc
#define  PHY_PINMUX_REG_REG_PAD_AOUTR1_PU_EN_OFFSET 2
#define  PHY_PINMUX_REG_REG_PAD_AOUTR1_PU_EN_MASK   0x4
#define  PHY_PINMUX_REG_REG_PAD_AOUTR1_PU_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_AOUTR1_PD_EN   0xfc
#define  PHY_PINMUX_REG_REG_PAD_AOUTR1_PD_EN_OFFSET 3
#define  PHY_PINMUX_REG_REG_PAD_AOUTR1_PD_EN_MASK   0x8
#define  PHY_PINMUX_REG_REG_PAD_AOUTR1_PD_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_AOUTR1_PIN_SEL_EN   0xfc
#define  PHY_PINMUX_REG_REG_PAD_AOUTR1_PIN_SEL_EN_OFFSET 4
#define  PHY_PINMUX_REG_REG_PAD_AOUTR1_PIN_SEL_EN_MASK   0xf0
#define  PHY_PINMUX_REG_REG_PAD_AOUTR1_PIN_SEL_EN_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_AOUTR1_DRI_SEL   0xfc
#define  PHY_PINMUX_REG_REG_PAD_AOUTR1_DRI_SEL_OFFSET 8
#define  PHY_PINMUX_REG_REG_PAD_AOUTR1_DRI_SEL_MASK   0xf00
#define  PHY_PINMUX_REG_REG_PAD_AOUTR1_DRI_SEL_BITS   0x4
#define  PHY_PINMUX_REG_REG_PAD_AOUTR1_SCT_EN   0xfc
#define  PHY_PINMUX_REG_REG_PAD_AOUTR1_SCT_EN_OFFSET 12
#define  PHY_PINMUX_REG_REG_PAD_AOUTR1_SCT_EN_MASK   0x1000
#define  PHY_PINMUX_REG_REG_PAD_AOUTR1_SCT_EN_BITS   0x1
#define  PHY_PINMUX_REG_REG_PAD_AOUTR1_OEX_EN   0xfc
#define  PHY_PINMUX_REG_REG_PAD_AOUTR1_OEX_EN_OFFSET 13
#define  PHY_PINMUX_REG_REG_PAD_AOUTR1_OEX_EN_MASK   0x2000
#define  PHY_PINMUX_REG_REG_PAD_AOUTR1_OEX_EN_BITS   0x1
